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document number: mc33889 rev. 12.0, 3/2007 freescale semiconductor technical data freescale semiconductor, inc. reserves the right to change the detai l specifications, as may be required, to permit improvements in the design of its products. ? freescale semiconductor, in c., 2007. all rights reserved. system basis chip with low speed fault tolerant can interface an sbc device is a monolithic i c combining many functions repeatedly found in standard microcontroller-based systems, e.g., protection, diagnostics, communicatio n, power, etc. the 33889 is an sbc having fully protected, fixed 5.0 v low drop-out regulator, with current limit, over-temperature pre-warning and reset. an output drive with sense input is also provided to implement a second 5.0 v regulator using an external pnp. the 33889 has normal, standby, stop and sleep modes; an internally switched high-side power supply output with two wake-up inputs; programmable timeout or window watchdog, interrupt, reset, spi input control, and a low- speed fault tolerant can transceiver, compatible with can 2.0 a and b protocols for module-to-module communications. the combination is an economical solution for power management, high-speed communication, a nd control in mcu-based systems. features ? vdd1: 5.0 v low drop voltage regulat or, current limitation, overtemperature detection, monitoring and reset function with total current capability 200 ma ?v 2 : tracking function of vdd1 regulator ; control circuitry for external bipolar ballast transistor for high flexibility in choice of peripheral voltage and current supply ? four operational modes ? low standby current consumpt ion in stop and sleep modes ? built-in low speed 125 kbps fault tolerant can physical interface. ? external high voltage wake-up input, associated with hs1 vbat switch ?150 ma output current capability for hs1 vbat switch allowing drive of external switches pull-up resistors or relays ? pb-free packaging designated by suffix code eg figure 1. 33889 simplified application diagram system basis chip 33889 * recommended for new designs ordering information device temperature range (t a ) package mc33889bdw/r2 -40c to 125c 28 soicw MCZ33889BEG/r2 mc33889ddw/r2 *mcz33889deg/r2 dw suffix eg suffix (pb-free) plastic package 98asb42345b 28-pin soicw local module supply safe circuits 33889 v mosi sclk miso spi cs wake-up inputs 5.0 v mcu v pwr can bus twisted pair hs1 wdog vdd1 int rst mosi sclk miso txd rxd gnd vsup l0 l1 v2ctrl v2 canh canl rth rtl cs 2
analog integrated circuit device data 2 freescale semiconductor 33889 device variations device variations table 1. device variations between the 33889d and 33889b versions (1) parameters symbol trait device part number mc33889b (2) mc33889d (2) differential receiver, recess ive to dominant threshold (by definition, v diff = v canh -v canl ) v diff1 min 3.2 v 3.5 v typ 2.6 v 3.0 v max 2.1 v 2.5 v differential receiver, dominant to recessive threshold (bus failures 1, 2, 5) v diff2 min 3.2 v 3.5 v typ 2.6 v 3.0 v max 2.1 v 2.5 v canh output current (v canh = 0; tx = 0.0) i canh min 50 ma 50 ma typ 75 ma 100 ma max 110 ma 130 ma canl output current (v canl = 14 v; tx = 0.0) i canl min 50 ma 50 ma typ 90 ma 140 ma max 135 ma 170 ma detection threshold for short circuit to battery voltage vcanh max vsup/2 + 5v vsup/2 + 4.55v loop time tx to rx, no bus failure, iso configuration tlooprd max n/a 1.5us loop time tx to rx, with bus failure, iso configuration tlooprd-f max n/a 1.9us loop time tx to rx, with bus failure and +-1.5v gnd shift, 5 node network, iso configuration tlooprd/dr-f+gs n/a 3.6us minimum dominant time for wake up on canl or canh (tem vbat mode) twake min n/a 8 typ 30 16 max n/a 30 t2spi timing t2spi min not specified, 25us spec applied 25us device behavior canh or canl open wire recovery principle reference mc33889b: on page 33 after 4 non consecutive pulses after 4 consecutive pulses rx behavior in termvbat mode reference mc33889d: on page 34 rx recessive, no pulse rx recessive, dominant pulse to signal bus traffic notes 1. this datasheet uses the term 33889 in t he inclusive sense, referring to both t he d version (33889d) and the b version (33689b ). 2. the 33889d and 33889b versions are nearly identical. however, where variations in characteristic occur, these items will be s eparated onto individual lines.
analog integrated circuit device data freescale semiconductor 3 33889 internal block diagram internal block diagram can h can l rth rtl tx rx oscillator mode control hs1 control fault tolerant can transceiver programmable wake-up inputs spi interface interrupt watchdog reset dual voltage regulator v sup voltage monitor v dd1 voltage monitor vdd1 int wdog vsup hs1 cs mosi miso sclk l1 l0 gnd v sup rst v 2 v2 v2ctrl 33889 internal block diagram
analog integrated circuit device data 4 freescale semiconductor 33889 pin connections pin connections figure 2. 33889 pin connections table 2. pin definitions a functional description of each pin can be found in the functional pin description section page 24 . pin pin name pin function formal name definition 1 rx output receiver data can bus receive data output pin 2 tx input transmitter data can bus receive data input pin 3 vdd1 power output voltage regulator one 5.0 v pin is a 2% low drop voltage regulator for to the microcontroller supply. 4 rst output reset this is the device reset output pin whose main function is to reset the mcu. 5 int output interrupt this output is asserted low when an enabled interrupt condition occurs. 6 -9, 20 - 23 gnd ground ground these device ground pins are internal ly connected to the package lead frame to provide a 33889-to-pcb thermal path. 10 v2ctrl output voltage source 2 control output drive source for the v2 regulat or connected to the external series pass transistor. 11 vsup power input voltage supply supply input pin. 12 hs1 output high-side output output of the internal high-side switch. 13 - 14 l0, l1 input level 0 - 1 inputs inputs from external switches or from logic circuitry. 15 v2 input voltage regulator two 5.0 v pin is a low drop voltage regulator dedicated to the peripherals supply. 16 rth output rth pin for connection of the bus termination resistor to canh. 17 rtl output rtl pin for connection of the bus termination resistor to canl. 18 canh output can high can high output pin. 19 canl output can low can low output pin. 24 sclk input system clock clock input pin for the serial peripheral interface (spi). wdog miso sclk gnd gnd gnd gnd canl canh rtl rth v2 cs mosi rx rst int gnd gnd gnd gnd v2ctrl vsup hs1 l0 l1 tx vdd1 4 5 6 7 8 9 10 11 12 13 14 2 3 28 25 24 23 22 21 20 19 18 17 16 15 27 26 1
analog integrated circuit device data freescale semiconductor 5 33889 pin connections 25 miso output master in/slave out spi data sent to the mcu by the 33889. when cs low is high, the pin is in the high impedance state. 26 mosi input master out/slave in spi data received by the 33889. 27 cs input chip select the cs low input pin is used with the spi bus to select the 33889. when the cs low is asserted low, the 33889 is the selected device of the spi bus. 28 wdog output watchdog the wdog output pin is asserted low if the software watchdog is not correctly triggered. table 2. pin defi nitions (continued) a functional description of each pin can be found in the functional pin description section page 24 . pin pin name pin function formal name definition
analog integrated circuit device data 6 freescale semiconductor 33889 electrical characteristics maximum ratings electrical characteristics maximum ratings table 3. maximum ratings all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. ratings symbol max unit electrical ratings supply voltage at vsup continuous voltage transient voltage (load dump) v sup -0.3 to 27 40 v logic signals (rx, tx, mosi, miso, cs , sclk, rst , wdog , int ) v log -0.3 to v dd1 +0.3 v output current vdd1 i internally limited ma hs1 voltage output current v i -0.2 to v sup +0.3 internally limited v a l0, l1 dc input voltage dc input current transient input voltage (according to iso7637 specification) and with external component per figure 3 . v wu i wu v trwu -0.3 to 40 -2.0 to 2.0 +-100 v ma v dc voltage at v2 (v2int) v 2int 0 to 5.25 v dc voltage on pins canh, canl v bus -20 to +27 v transient voltage at pins canh, canl 0.0 < v2-int < 5.5 v; vsup = 0.0; t < 500 ms v canh /v canl -40 to +40 v transient voltage on pins canh, canl (coupled through 1.0 nf capacitor) v tr -150 to +100 v dc voltage on pins rth, rtl v rtl , v rth -0.3 to +27v v transient voltage at pins rth, rtl 0.0 < v2-int < 5.5 v; vsup = 0.0; t < 500 ms v rth /v rtl -0.3 to +40 v
analog integrated circuit device data freescale semiconductor 7 33889 electrical characteristics maximum ratings esd voltage (hbm 100 pf, 1.5 k) (3) canl, canh, hs1, l0, l1 rth, rtl all other pins v esdh 4.0 3.0 2.0 kv esd voltage (machine model) all pins, mc33889b (3) (4) v esd-mm 200 v esd voltage (cdm) all pins, mc33889d (4) pins 1,14,15, & 28 all other pins v esd-cdm 750 500 v rth, rtl termination resistance r t 500 to 16000 ohms thermal ratings junction temperature t j -40 to 150 c storage temperature t s -55 to 165 c ambient temperature (for info only) t a -40 to 125 c thermal resistance junction to gnd pin (5) r thj/p 20 c/w notes: 3. testing done in accordance with the human body model (c zap =100 pf, r zap =1500 ), machine model (c zap =200 pf, r zap =0 ). 4. esd machine model (mm) is for mc33889b only. mm is now replaced by cdm (charged discharged model). 5. gnd pins 6,7,8,9,20, 21, 22, 23. figure 3. transient test pulse for l0 and l1 inputs table 3. maximum ratings (continued) all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. ratings symbol max unit lx transient pulse gnd gnd generator 1nf note: waveform in accordance to iso7637 part1, test pulses 1, 2, 3a and 3b. (note) 10 k
analog integrated circuit device data 8 freescale semiconductor 33889 electrical characteristics static electrical characteristics static electrical characteristics table 4. static electric al characteristics . characteristics noted under conditions - v sup from 5.5 v to 18 v and t j from -40c to 125c, unle ss otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions unless otherwise noted. description symbol min typ max unit input pin (vsup) nominal dc voltage range v sup 5.5 - 18 v extended dc voltage range 1 reduced functionality (6) v sup-ex1 4.5 - 5.5 v extended dc voltage range 2 (8) v sup-ex2 18 - 27 v input voltage during load dump load dump situation v supld - - 40 v input voltage during jump start jump start situation v supjs - - 27 v supply current in sleep mode (7) v dd1 & v2 off, v sup 12 v, oscillator running (10) i sup (sleep1) - 95 130 a supply current in sleep mode (7) v dd1 & v2 off, v sup 12 v, oscillator not running i sup (sleep2) - 55 90 a supply current in sleep mode (7) v dd1 & v2 off, v sup = 18 v, oscillator running (10) i sup (sleep3) - 170 270 a supply current in stand-by mode (7) , (9) iout at v dd1 = 40 ma, can recessive state or disabled i sup ( stdby ) - 42 45 ma supply current in normal mode (7) iout at v dd1 = 40 ma, can recessive state or disabled i sup(norm) - 42.5 45 ma supply current in stop mode (7) , (9) i out v dd1 < 2.0 ma, v dd1 on (11) , v sup 12 v, oscillator running (10) i sup (stop1) - 120 150 a supply current in stop mode (7) , (9) iout v dd1 < 2.0 ma, v dd1 on (11) v sup 12v, oscillator not running (10) i sup (stop2) - 80 110 a supply current in stop mode (7) , (9) iout v dd1 < 2.0 ma, v dd1 on (11) , v sup = 18 v, oscillator running (10) i sup (stop3) - 200 285 a notes 6. v dd1 > 4.0 v, reset high, if r stth-2 selected and i out v dd1 reduced, logic pin high level reduced, device is functional. 7. current measured at v sup pin. 8. device is fully functional. al l modes available and operating, watchdog, hs1 turn on turn off, can cell operating, l0 and l1 inputs operating, spi read write operation. over temperature may occur. 9. measured in worst case condition with 5.0 v at v2 pin (v2 pin tied to vdd1). 10. oscillator running means ?forced wake-u p? or ?cyclic sense? or ?software watc hdog? timer activated. software watchdog is available in stop mode only. 11. v dd1 is on with 2.0 ma typi cal output current capability.
analog integrated circuit device data freescale semiconductor 9 33889 electrical characteristics static electrical characteristics supply fail flag internal threshold v thresh 1.5 3.0 4.0 v supply fail flag hysteresis (12) v dethyst - 1.0 - v battery fall early warning threshold in normal & standby mode bf ew 5.8 6.1 6.4 v battery fall early warning hysteresis in normal & standby mode (12) bf ewh 0.1 0.2 0.3 v output pin (vdd1) (13) vdd1 output voltage i dd1 from 2.0 to 200ma 5.5 v < v sup < 27 v 4.5 v < v sup < 5.5 v v dd1out 4.9 4.0 5.0 - 5.1 - v drop voltage v sup > v ddout i dd1 = 200 ma v dd1drop - 0.2 0.5 v drop voltage v sup > v ddout , limited output current i dd1 = 50 ma 4.5 v < v sup < 27 v v dd1dp2 - 0.1 0.25 v i dd1 output current internally limited i dd1 200 270 350 ma vdd1 output voltage in stop mode iout < 2.0 ma v ddstop 4.75 5.00 5.25 v i dd1 stop output current to wake-up sbc default value after reset. (14) i dd1s-wu1 2.0 3.5 6.0 ma i dd1 stop output current to wake-up sbc (14) i dd1s-wu2 10 14 18 ma i dd1 over current wake deglitcher (with i dd1s-wu1 selected) (12) i dd1-dgit11 40 55 75 s i dd1 over current wake deglitcher (with i dd1s-wu2 selected) (12) i dd1-dgit2 - 150 - s thermal shutdown normal or standby mode t sd 160 - 190 c over temperature pre warning vddtemp bit set t pw 130 - 160 c temperature threshold difference t sd -t pw 20 - 40 c notes 12. guaranteed by design 13. i dd1 is the total regulator output current. vdd specification with ex ternal capacitor c 22 f and esr < 1o ohm. 14. selectable by spi table 4. static electrical characteristics (continued) . characteristics noted under conditions - v sup from 5.5 v to 18 v and t j from -40c to 125c, unle ss otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions unless otherwise noted. description symbol min typ max unit
analog integrated circuit device data 10 freescale semiconductor 33889 electrical characteristics static electrical characteristics reset threshold 1 default value after reset. (15) v rst-th1 4.5 4.6 4.7 v reset threshold 2 (15) v rst-th2 4.1 4.2 4.3 v reset duration reset-dur 0.85 1.0 2.0 ms vdd1 range for reset active v dd 1.0 - - v reset delay time measured at 50% of reset signal. (16) t d 5.0 - 20 s line regulation 9.0 v < v sup < 18, i dd = 10 ma lr1 - 5.0 25 mv line regulation 5.5 v < v sup < 27 v, i dd = 10 ma lr2 - 10 25 mv load regulation 1 ma < i idd < 200 ma ld - 25 75 mv thermal stability v sup = 13.5 v, i = 100 ma therms - 5.0 - mv v2 regulator (v2) (17) v2 output voltage i2 from 2.0 to 200 ma 5.5 v < v sup < 27 v v2 0.99 1.0 1.01 v dd1 i2 output current (for information only) depending on the external ballast transistor i2 200 - - ma v2 ctrl sink current capability i2 ctrl 10 - - ma v2low flag threshold v2l th 3.75 4.0 4.25 v internal v2 supply current (can and sbc in normal mode). tx = 5.0 v, can in recessive state i v2rs 3.8 5.6 6.8 ma internal v2 supply current (can and sbc in normal mode). tx = 0.0 v, no load, can in dominant state i v2ds 4.0 5.8 7.0 ma internal v2 supply current (can in receive only mode, sbc in normal mode). v sup = 12 v i v2r 80 120 a internal v2 supply current (can in bus termvbat mode, sbc in normal mode), v sup = 12 v i v2bt 35 60 a notes 15. selectable by spi 16. guaranteed by design 17. v2 tracking voltage regulator - v2 specification with external capacitor - option 1: c 22 f and esr < 10 ohm. using a resistor of 2 kohm or le ss between the base and emitter of the external pnp is recommended. - option2: 1.0 f < c < 22 f and esr < 10 ohm. in this case depending on the ballast transistor gain an additional resistor and capacitor network between emitter and base of pnp ballast trans istor might be required. refer to freescale application informat ion or contact your local technical support. - option 3: 10uf < c < 22uf esr > 0.2 ohms: a resistor of 2 kohm or less is required between the base and emitter of the extern al pnp. table 4. static electrical characteristics (continued) . characteristics noted under conditions - v sup from 5.5 v to 18 v and t j from -40c to 125c, unle ss otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions unless otherwise noted. description symbol min typ max unit
analog integrated circuit device data freescale semiconductor 11 33889 electrical characteristics static electrical characteristics logic output pins (miso) low level output voltage i out = 1.5 ma v ol - - 1.0 v high level output voltage i out = -250 a v oh v dd1-0.9 - - v tri-state miso leakage current 0.0 v < v miso < v dd i hz -2.0 - +2.0 a logic input pins (mosi, sclk, cs ) high level input voltage v ih 0.7v dd1 - v dd1 +0.3v low level input voltage v il -0.3 - 0.3 v dd1 v input current on cs v i = 4.0 v v i = 1.0 v i ih i il -100 - -20 a low level input current cs v i = 1.0 v i il -100 - -20 a mosi, sclk input current 0.0 < v in < v dd i in -10 - 10 a reset pin ( rst ) high level output current 0.0 < v out < 0.7 v dd i oh -350 -250 -150 a low level output voltage (i 0 = 1.5 ma) 5.5 v < v sup < 27 v 1.0 v < v dd1 v ol 0.0 0.0 - - 0.9 0.9 v reset pull down current i pdw 2.3 - 5.0 ma watchdog pin ( wdog ) low level output voltage (i 0 = 1.5 ma) 5.5 v < v sup < 27 v v ol 0.0 - 0.9 v high level output voltage (i 0 = -250 a) v oh v dd1 -0.9 - v dd1 v interrupt pin ( int ) low level output voltage (i 0 = 1.5 ma) v ol 0.0 - 0.9 v high level output voltage (i 0 = -250 a) v oh v dd1 -0.9 - v dd1 v high-side output pin (hs1) r dson at tj = 25c, and i out -150 ma v sup >9v r dson25 - - 2.5 ohms table 4. static electrical characteristics (continued) . characteristics noted under conditions - v sup from 5.5 v to 18 v and t j from -40c to 125c, unle ss otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions unless otherwise noted. description symbol min typ max unit
analog integrated circuit device data 12 freescale semiconductor 33889 electrical characteristics static electrical characteristics r dson at tj = 125c, and i out -150 ma v sup > 9.0 v r dson125 - - 5.0 ohms r dson at tj = 125c, and i out -120 ma 5.5 v < v sup < 9.0 v r don125-2 - 4.0 5.5 ohms output current limitation i lim 160 - 500 ma over temperature shutdown o vt 155 - 190 c leakage current i leak - - 10 a output clamp voltage at i out = -1.0 ma (18) no inductive load drive capability v cl -1.5 - -0.3 v input pins (l0 and l1) l0 negative switching threshold 5.5 v < v sup < 6.0 v 6.0 v < v sup < 18 v 18 v < v sup < 27 v v th0n 1.7 2.0 2.0 2.0 2.4 2.5 3.0 3.0 3.1 v l0 positive switching threshold 5.5 v < v sup < 6.0 v 6.0 v < v sup < 18 v 18 v < v sup < 27 v v th0p 2.2 2.5 2.5 2.75 3.4 3.5 4.0 4.0 4.1 v l1 negative switching threshold 5.5 v < v sup < 6.0 v 6.0 v < v sup < 18 v 18 v < v sup < 27 v v th1n 2.0 2.5 2.7 2.5 3.0 3.2 3.0 3.7 3.8 v l1 positive switching threshold 5.5 v < v sup < 6.0 v 6.0 v < v sup < 18v 18 v < v sup < 27 v v th1p 2.7 3.0 3.5 3.3 4.0 4.2 3.8 4.7 4.8 v hysteresis 5.5 v < v sup < 27 v v hyst 0.6 1.0 1.3 v input current -0.2 v < v in < 40 v i in -10 - 10 a can module specification (tx, rx, canh, canl, rth, and rtl) dc voltage on pins tx, rx v logic -0.3 v dd1 + 0.3 v dc voltage at v2 (v2int) v2 int 0.0 5.25 v dc voltage on pins canh, canl v bus -20 +27 v notes 18. refer to hs1 negative maximum rating voltage limitation of -0.2v. table 4. static electrical characteristics (continued) . characteristics noted under conditions - v sup from 5.5 v to 18 v and t j from -40c to 125c, unle ss otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions unless otherwise noted. description symbol min typ max unit
analog integrated circuit device data freescale semiconductor 13 33889 electrical characteristics static electrical characteristics transient voltage at pins canh, canl 0.0 < v 2-int < 5.5 v; v sup 0.0; t < 500 ms v canh /v canl -40 40 v transient voltage on pins canh, canl (coupled through 1.0 nf capacitor) v tr -150 100 v detection threshold for short-circuit to battery voltage (term vbat mode) mc33889b v canh v sup /2+3 v sup /2+5 v detection threshold for short-circuit to battery voltage (term vbat mode) mc33889d v canh v sup /2+3 v sup / 2+4.55 v dc voltage on pins rth, rtl v rtl , v rth -0.3 +27 v transient voltage at pins rth, rtl 0.0 < v 2-int < 5.5 v; v sup 0.0; t < 500 ms v rth /v rtl -0.3 40 v transmitter data pin (tx) high level input voltage v ih 0.7*v 2 v 2 +0.3v v low level input voltage v il -0.3 0.3 * v 2 v tx high level input current (v i = 4.0 v) i txh -100 -50 -25 a tx low level input current (v i = 1.0 v) i txl -100 -50 -25 a receive data pin (rx) high level output voltage rx (i 0 = -250 a) v oh v 2-int - 0.9 v 2-int v low level output voltage (i 0 = 1.5 ma) v ol 0.0 0.9 v can high and can low pins (canh, canl) differential receiver, recess ive to dominant threshold (by definition, v diff = v canh -v canl ) for 33889d for 33889b v diff1 -3.5 -3.2 -3.0 -2.6 -2.5 -2.1 v differential receiver, dominant to recessive threshold (bus failures 1, 2, 5) for 33889d for 33889b v diff2 -3.5 -3.2 -3.0 -2.6 -2.5 -2.1 v canh recessive output voltage tx = 5.0 v; r (rth) < 4.0 k v canh 0.2 v canl recessive output voltage tx = 5.0 v; r (rtl) < 4.0 k v canl v 2-int - 0.2 v table 4. static electrical characteristics (continued) . characteristics noted under conditions - v sup from 5.5 v to 18 v and t j from -40c to 125c, unle ss otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions unless otherwise noted. description symbol min typ max unit
analog integrated circuit device data 14 freescale semiconductor 33889 electrical characteristics static electrical characteristics canh output voltage, dominant tx = 0.0 v; i canh = -40 ma; normal operating mode (19) v canh v 2 - 1.4 v canl output voltage, dominant tx = 0.0 v; i canl = 40 ma; normal operating mode (19) v canl 1.4 v canh output current (v canh = 0; tx = 0.0) for 33889d for 33889b i canh 50 50 100 75 130 110 ma canl output current (v canl = 14 v; tx = 0.0) for 33889d for 33889b i canl 50 50 140 90 170 135 ma detection threshold for short-circuit to battery voltage (normal mode) v canh , v canl 7.3 7.9 8.9 v detection threshold for short-circuit to battery voltage (term vbat mode), mc33889b vcanh vsup/2+3 vsup/2+5 v detection threshold for short-circuit to battery voltage (term vbat mode), mc33889d vcanh vsup/2+3 vsup/ 2+4.55 v canh output current (term v bat mode; v canh = 12 v, failure3) i canh 5.0 10 a canl output current (term v bat mode; v canl = 0.0 v; v bat = 12 v, failure 4) i canl 0.0 2.0 a canl wake-up voltage threshold v wake,l 2.5 3.0 3.9 v canh wake-up voltage threshold v wake,h 1.2 2.0 2.7 v wake-up threshold di fference (hysteresis) v wakel - v wakeh 0.2 v canh single ended receiver threshold (failures 4, 6, 7) v se, canh 1.5 1.85 2.15 v canl single ended receiver threshold (failures 3, 8) v se, canl 2.8 3.05 3.4 v canl pull up current (normal mode) i canl,pu 45 75 90 a canh pull down current (normal mode) i canh,pd 45 75 90 a receiver differential input impedance canh / canl r diff 100 300 kohm differential receiver common mode voltage range (20) v com -10 10 v canh to ground capacitance c canh 50 pf canl to ground capacitance c canl 50 pf c canl to c canh capacitor difference dc can 10 pf can driver thermal shutdown t csd 150 160 c notes 19. for mc33889b, after 128 pulses on tx and no bus failure. 20. guaranteed by design table 4. static electrical characteristics (continued) . characteristics noted under conditions - v sup from 5.5 v to 18 v and t j from -40c to 125c, unle ss otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions unless otherwise noted. description symbol min typ max unit
analog integrated circuit device data freescale semiconductor 15 33889 electrical characteristics static electrical characteristics bus termination pins (rth, rtl) rtl to v2 switch on resistance (i out < -10 ma; normal operating mode) r rtl 10 30 90 ohms rtl to bat switch series resistance (term v bat mode) r rtl 8.0 12.5 20 kohm rth to ground switch on resistance (i out < 10 ma; normal operating mode) r rth 10 30 90 ohm table 4. static electrical characteristics (continued) . characteristics noted under conditions - v sup from 5.5 v to 18 v and t j from -40c to 125c, unle ss otherwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions unless otherwise noted. description symbol min typ max unit
analog integrated circuit device data 16 freescale semiconductor 33889 electrical characteristics dynamic electrical characteristics dynamic electrical characteristics table 5. dynamic electri cal characteristics v sup from 5.5 v to 18 v, v2int from 4.75 to 5.25 v and t j from -40c to 150c unless ot herwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions unless otherwise noted. conditions symbol min typ max unit digital interface timing (sclk, cs , mosi, miso) spi operation frequency freq - - 4.0 mhz sclk clock period t pclk 250 - - ns sclk clock high time t wsclkh 125 - - ns sclk clock low time t wsclkl 125 - - ns falling edge of cs to rising edge of sclk t llead 100 50 - ns falling edge of sclk to rising edge of cs t lag 100 50 - ns mosi to falling edge of sclk t sisu 40 25 - ns falling edge of sclk to mosi t sih 40 25 - ns miso rise time (cl = 220 pf) t rso - 25 50 ns miso fall time (cl = 220 pf) t fso - 25 50 ns time from falling or rising edges of cs to: - miso low impedance - miso high impedance t soen t sodis - - 50 50 ns time from rising edge of sclk to miso data valid 0.2 v1 so 0.8 v1, c l = 200 pf t valid - - 50 ns delay between cs low to high transition (at end of spi stop command) and stop or sleep mode activation (21) detected by v2 off t cs -stop 18 - 34 s interrupt low level duration sbc in stop mode t int 7.0 10 13 s internal oscillator frequency all modes except sleep and stop (21) o sc-f1 - 100 - khz notes 21. guaranteed by design
analog integrated circuit device data freescale semiconductor 17 33889 electrical characteristics dynamic electrical characteristics internal low power oscillator frequency sleep and stop modes (22) o sc-f2 - 100 - khz watchdog period 1 normal and standby modes w d1 8.58 9.75 10.92 ms watchdog period 2 normal and standby modes w d2 39.6 45 50.4 ms watchdog period 3 normal and standby modes w d3 88 100 112 ms watchdog period 4 normal and standby modes w d4 308 350 392 ms watchdog period accuracy normal and standby modes f1 acc -12 - 12 % normal request mode timeout normal request mode nr tout 308 350 392 ms watchdog period 1 - stop stop mode wd1 stop 6.82 9.75 12.7 ms watchdog period 2- stop stop mode wd2 stop 31.5 45 58.5 ms watchdog period 3 - stop stop mode wd3 stop 70 100 130 ms watchdog period 4 - stop stop mode wd4 stop 245 350 455 ms stop mode watchdog period accuracy stop mode f2 acc -30 - 30 % cyclic sense/ fwu timing 1 sleep and stop modes csfwu1 3.22 4.6 5.98 ms cyclic sense/ fwu timing 2 sleep and stop modes csfwu2 6.47 9.25 12 ms notes 22. guaranteed by design table 5. dynamic electrical characteristics (continued) v sup from 5.5 v to 18 v, v2int from 4.75 to 5.25 v and t j from -40c to 150c unless ot herwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions unless otherwise noted. conditions symbol min typ max unit
analog integrated circuit device data 18 freescale semiconductor 33889 electrical characteristics dynamic electrical characteristics cyclic sense/ fwu timing 3 sleep and stop modes csfwu3 12.9 18.5 24 ms cyclic sense/ fwu timing 4 sleep and stop modes csfwu4 25.9 37 48.1 ms cyclic sense/ fwu timing 5 sleep and stop modes csfwu5 51.8 74 96.2 ms cyclic sense/ fwu timing 6 sleep and stop modes csfwu6 66.8 95.5 124 ms cyclic sense/ fwu timing 7 sleep and stop modes csfwu7 134 191 248 ms cyclic sense/ fwu timing 8 sleep and stop modes csfwu8 271 388 504 ms cyclic sense on time in sleep and stop modes t on 200 300 400 s cyclic sense/fwu timing accuracy in sleep and stop mode t acc -30 - +30 % delay between spi command and hs1 turn on (23) normal or standby mode, v sup > 9.0 v t s-hson - - 22 s delay between spi command and hs1 turn off (23) normal or standby mode, v sup > 9.0 v t s-hsoff - - 22 s delay between spi and v2 turn on (23) standby mode t s-v2on 9.0 - 25 s delay between spi and v2 turn off (23) normal modes t s-v2off 9.0 - 25 s delay between normal request and normal mode, after w/d trigger command normal request mode t s-nr2n 15 35 70 s notes 23. state machine timing - delay starts at rising edge of cs (end of spi command) and start of turn on or turn off of hs1 or v2. table 5. dynamic electrical characteristics (continued) v sup from 5.5 v to 18 v, v2int from 4.75 to 5.25 v and t j from -40c to 150c unless ot herwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions unless otherwise noted. conditions symbol min typ max unit
analog integrated circuit device data freescale semiconductor 19 33889 electrical characteristics dynamic electrical characteristics delay between spi and ?can normal mode? sbc normal mode (24) t s-cann - - 10 s delay between spi and ?can sleep mode? sbc normal mode (24) t s-cans - - 10 s delay between cs wake-up ( cs low to high) and sbc normal request mode (v dd1 on & reset high) sbc in stop mode t w- cs 15 40 90 s delay between cs wake-up ( cs low to high) and first accepted spi command sbc in stop mode t w-spi 90 - - s delay between int pulse and 1st spi command accepted in stop mode after wake-up t s-1stspi 20 - - s delay between two spi messages addressing the same register for 33889d only t2 spi 25 - - s input pins (l0 and l1) wake-up filter time (enable/disable option on l0 input) (if filter enabled) t wuf 8.0 20 38 s pin ac characteristics (canh, canl, rx, tx) canl and canh slew rates (25% to 75% can signal). (25) recessive to dominant state dominant to recessive state t sldr 2.0 2.0 8.0 9.0 v/ s propagation delay tx to rx low. -40c < t 25c. (26) tx to rx low. 25c < t < 125c. (26) t onrx 1.2 1.1 1.6 1.8 s propagation delay tx to rx high. (26) t offrx 1.8 2.2 s notes 24. guaranteed by design 25. dominant to recessive slew rate is dependant upon the bus load characteristics. 26. ac characteristics measur ed according to schematic figure 4 table 5. dynamic electrical characteristics (continued) v sup from 5.5 v to 18 v, v2int from 4.75 to 5.25 v and t j from -40c to 150c unless ot herwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions unless otherwise noted. conditions symbol min typ max unit
analog integrated circuit device data 20 freescale semiconductor 33889 electrical characteristics dynamic electrical characteristics loop time tx to rx, no bus failure, mc33889d only ( (27) , figure 5 ) (iso ict test series 10) tx high to low transition (dominant edge) tx low to high transition (recessive edge) t looprd 1.15 1.45 1.5 1.5 s loop time tx to rx, with bus failure, mc33889d only ( (27) , figure 6 ) (iso ict test series 10) tx high to low transition (dominant edge) tx low to high transition (recessive edge) t looprd-f - - 1.9 1.9 s loop time tx to rx, with bus failure and +-1.5v gnd shift, 5 nodes network, mc33889d,( (28) , figure 7 , iso ict tests series 11) t looprd/dr-f+gs 3.6 s min. dominant time for wake-up on canl or canh (term vbat; v sup = 12v) guaranteed by design. mc33889b mc33889d t wake 8.0 30 16 30 s failure 3 detection time (normal mode) t df3 10 30 80 s failure 3 recovery time (normal mode) t dr3 160 s failure 6 detection time (normal mode) t df6 50 200 500 s failure 6 recovery time (normal mode) t dr6 150 200 1000 s failure 4, 7 detection time (normal mode) t df47 0.75 1.5 4.0 ms failure 4, 7 recovery time (normal mode) t dr47 10 30 60 s failure 3a, 8 detection time (normal mode) t df8 0.75 1.7 4.0 ms failure 3a, 8 recovery time (normal mode) tt dr8 0.75 1.5 4.0 ms failure 4, 7 detection time, (term v bat ; v sup = 12 v) t dr47 0.8 1.2 8.0 ms failure 4, 7 recovery time (term v bat ; v sup = 12 v) t dr47 1.92 ms failure 3 detection time (term v bat ; v sup = 12 v) t dr3 3.84 ms failure 3 recovery time (term v bat ; v sup = 12 v) t dr3 1.92 ms failure 3a, 8detection time (term v bat ; v sup = 12 v) t dr8 2.3 ms failure 3a, 8 recovery time (term v bat ; v sup = 12 v) t dr8 1.2 ms notes 27. ac characteristic according to iso11898-3, tested per figure 5 and 6. guaranteed by design, room temperature only. 28. ac characteristic according to iso11898-3, tested per figure 7. max reported is the typical measurement under the worst cond ition (gnd shift, dominant/recessive edge, at source or destination node. ref to iso test specification). guarant eed by design, room temperature only. table 5. dynamic electrical characteristics (continued) v sup from 5.5 v to 18 v, v2int from 4.75 to 5.25 v and t j from -40c to 150c unless ot herwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions unless otherwise noted. conditions symbol min typ max unit
analog integrated circuit device data freescale semiconductor 21 33889 electrical characteristics dynamic electrical characteristics figure 4. test circuit for ac characteristics figure 5. iso loop time without bus failure figure 6. iso loop time with bus failure edge count difference between canh and canl for failures 1, 2, 5 detection (failure bit set, normal mode) e cdf 3 edge count difference between canh and canl for failures 1, 2, 5 recovery (normal mode) e cdr 3 tx permanent dominant timer disable time (normal mode and failure mode) t tx,d 0.75 4.0 ms tx permanent dominant timer enable time (normal mode and failure mode) t tx,e 10 60 s table 5. dynamic electrical characteristics (continued) v sup from 5.5 v to 18 v, v2int from 4.75 to 5.25 v and t j from -40c to 150c unless ot herwise noted. typical values noted reflect the approximate parameter means at t a = 25 c under nominal conditions unless otherwise noted. conditions symbol min typ max unit canh canl r r c c vdd c r = 100ohms c = 1nf canh canl 1nf 5v 1nf 500 500 rth rtl rx tx mc33889d rcanl rcanh rcanl = rcanh = 125 ohms canh canl 1nf 1nf 500 500 rth rtl rcanl rcanh rx tx mc33889d generator (*) bus failure vbat rcanl = rcanh = 125 ohms except for failure canh short to canl (rcanl = 1m ohms) canl short to gnd, vdd, vbat canhshort to gnd, vdd, vbat canl short to canh canl and canh open (*) list of failure
analog integrated circuit device data 22 freescale semiconductor 33889 electrical characteristics dynamic electrical characteristics figure 7. test set up for propagation dela y with gnd shift in a 5 node configuration
analog integrated circuit device data freescale semiconductor 23 33889 electrical characteristics timing diagrams timing diagrams figure 8. device signal waveforms figure 9. timing characteristic t v th(rd) v th(dr) 0.7v cc 0.3v cc t onrx t offrx -5.0v 2.2v v rx v diff v tx t offtx canh canl 5.0v 0.0v 3.6v 1.4v dominant bit recessive bit recessive bit tx high: recessive bit tx low: dominant bit tx high: recessive bit d0 d0 undefined don?t care d7 don?t care t lead t sih t sisu t lag t pclk t wclkh t wclkl t valid don?t care d7 t sodis cs sclk mosi miso t soen
analog integrated circuit device data 24 freescale semiconductor 33889 functional description introduction functional description introduction the mc33889 is an integrated circuit dedicated to automotive applications. it includes the following functions: ? one full protected voltage regulator with 200 ma total output current capability. ? driver for external path transistor for v2 regulator function. ? reset, programmable watchdog function ? four operational modes ? wake-up capabilities: forced wake-up, cyclic sense and wake-up inputs, can and the spi ? can low speed fault tolerant physical interface. functional pin description receive and transmit data (rx and tx) the rx and tx pins (receive data and transmit data pins, respectively) are connected to a microcontroller?s can protocol handler. tx is an input and controls the canh and canl line state (dominant when tx is low, recessive when tx is high). rx is an output and reports the bus state (rx low when can bus is dominant, high when can bus is recessive). voltage regulator one (vdd1) the vdd1 pin is the output pin of the 5.0 v internal regulator. it can deliver up to 200 ma. this output is protected against overcurrent and overtemperature. it includes an overtemperature pre-warning flag, which is set when the internal regulator temperature exceeds 130c typical. when the temperature exceeds th e overtemperature shutdown (170c typical), the regulator is turned off. vdd1 includes an undervoltage reset circui try, which sets the rst pin low when vdd is below the undervoltage reset threshold. reset ( rst ) the reset pin rst is an output that is set low when the device is in reset mode. the rst pin is set high when the device is not in reset mode. rst includes an internal pullup current source. when rst is low, the sink current capability is limited, allowing rst to be shorted to 5.0 v for software debug or software download purposes. interrupt ( int ) the interrupt pin int is an output that is set low when an interrupt occurs. int is enabled using the interrupt register (intr). when an interrupt occurs, int stays low until the interrupt source is cleared. int output also reports a wake-up event by a 10 sec. typical pulse when the device is in stop mode. ground (gnd) this pin is the ground of the integrated circuit. v2ctrl (v2ctrl) the v2ctrl pin is the output drive pin for the v2 regulator connected to the external series pass transistor. voltage supply (vsup) the vsup pin is the battery supply input of the device. high-side output 1 (hs1) the hs pin is the internal hi gh-side driver output. it is internally protected against overcurrent and overtemperature. level 0-1 inputs (l0: l1) the l0: l1 pins can be connected to contact switches or the output of other ics for external inputs. the input states can be read by the spi. these inputs can be used as wake- up events for the sbc when operating in the sleep or stop mode. voltage regulator two (v2) the v2 pin is the input sense for the v2 regulator. it is connected to the external series pass transistor. v2 is also the 5.0 v supply of the internal can in terface. it is possible to connect v2 to an external 5.0 v regulator or to the vdd output when no external series pass transistor is used. in this case, the v2ctrl pin must be left open. rth (rth) pin for the connection of the bus termination resistor to canh rtl (rtl) pin for the connection of the bus termination resistor to canl can high and can low outputs (canh and canl) the can high and can low pins are the interfaces to the can bus lines. they are contro lled by txd input level, and the state of canh and canl is reported through rxd output. system clock (sclk) sclk is the serial data clock input pin of the serial peripheral interface.
analog integrated circuit device data freescale semiconductor 25 33889 functional description functional internal block description master in/slave out (miso miso is the master in slave out pin of the serial peripheral interface. data is sent from the sbc to the microcontroller through the miso pin. master out/slave in (mosi) mosi is the master out slave in pin of the serial peripheral interface. control data from a microcontroller is received through this pin. chip select ( cs ) cs is the chip select pin of the serial peripheral interface. when this pin is low, the spi po rt of the device is selected. watch dog ( wdog) the watchdog output pin is asse rted low to flag that the software watchdog has not been properly triggered. functional internal block description device supply the device is supplied from the battery line through the vsup pin. an external diode is required to protect against negative transients and reverse battery. it can operate from 4.5 v and under the jump start condition at 27 v dc. this pin sustains standard automotive voltage conditions such as load dump at 40 v. when v sup falls below 3.0 v typical, the mc33889 detects it and stores the information in the spi register, in a bit called ?batfail ?. this detection is available in all operation modes. vdd1 voltage regulator vdd1 regulator is a 5.0 v output voltage with total current capability of 200 ma. it includes a voltage monitoring circuitry associated with a reset function. the vdd1 regulator is fully protected against overcurrent, short-circuit and has overtemperature detection warning flags and shutdown with hysteresis. v2 regulator v2 regulator circuitry is designed to drive an external path transistor in order to increase output current flexibility. two pins are used: v2 and v2ct rl. output voltage is 5.0 v and is realized by a tracking function of the vdd1 regulator. a recommended ballast transistor is the mjd32c. other transistors might be used, however depending upon the pnp gain, an external resistor capacitor network might be connected between the emitter and base of the pnp. the use of external ballast is optional (refer to simplified typical application). the state of v2 is reported into the ior register (if v2 is below 4.5 v typical, or in cases of overload or short- circuit). hs1 vbat switch output hs1 output is a 2.0 ohm typica l switch from the vsup pin. it allows the supply of external switches and their associated pullup or pull-down circuitry, for example, in conjunction with the wake-up input pins. output current is limited to 200 ma and hs1 is protected against short-circuit and has an over temperature shutdown (reported into the ior register). the hs1 output is controlled from the internal register and the spi. it can be activated at regular intervals in sleep mode thanks to an internal timer. it can also be permanently turned on in normal or stand-by modes to drive external loads, such as relays or supply peripheral components. in case of inductive load drive, external clamp circuitry must be added. spi the complete device control as well as the status report is done through an 8 bit spi interface. refer to the spi paragraph. can the device incorporates a low speed fault tolerant can physical interface. the speed rate is up to 125 kbauds. the state of the can interface is programmable through the spi. reference the can transceiver description on page 30 . package and thermal consideration the device is proposed in a standard surface mount so28 package. in order to improve th e thermal performances of the so28 package, 8 pins are internally connected to the lead frame and are used for heat transfer to the printed circuit board.
analog integrated circuit device data 26 freescale semiconductor 33889 functional device operation operational modes functional device operation operational modes introduction the device has four modes of operation, normal, stand-by, sleep and stop modes. all modes are controlled by the spi. an additional temporary mode called ?normal request mode? is automatically accessed by the device (refer to state machine) after wake-up events. special mode and configurations are possible for software application debug and flash memory programming. normal mode in this mode both regulators are on, and this corresponds to the normal application operation. all functions are available in this mode (watchdog, wake-up input reading through the spi, hs1 activati on, and can communication). the software watchdog is running and must be periodically cleared through the spi. standby mode only the regulator 1 is on. regulator 2 is turned off by disabling the v2ctrl pin. the can cell is not available, as powered from v2. other functions are available: wake-up input reading through the spi and hs1 activation. the watchdog is running. sleep mode regulators 1 and 2 are off. in this mode, the mcu is not powered. the device can be aw akened internally by cyclic sense via the wake-up input pins and hs1 output, from the forced wake function, the can physical interface, and the spi ( cs pin). stop mode regulator 2 is turned off by disabling the v2ctrl pin. regulator 1 is activated in a special low power mode which allows it to deliver 2.0 ma. the objective is to supply the mcu of the application while it is turned into a power saving condition (i.e stop or wait mode). stop mode is entered through the spi. stop mode is dedicated to powering the microc ontroller when it is in low power mode (stop, pseudo stop, wait etc.). in these modes, the mcu supply current is less than 1.0 ma. the mcu can restart its software applicat ion very quickly without the complete power up and reset sequence. when the application is in stop mode (both mcu and sbc), the application can wake-up from the sbc side (ex cyclic sense, forced wake -up, can message, wake-up inputs) or the mcu side (key wake-up etc.). when stop mode is selected by the spi, stop mode becomes active 20 s after end of the spi message. the ?go to stop? instruction must be the last instruction executed by the mcu before going to low power mode. in stop mode, the software watchdog can be ?running? or ?not running? depending on the selection by the spi. refer to the spi description, rcr register bit wdstop. if the w/d is enabled, the sbc must wake-up before the w/d time has expired, otherwise a reset is generated. in stop mode, the sbc wake-up capability is identical as in sleep mode. stop mode: wake-up from sbc side, int pin activation when an application is in stop mode, it can wake-up from the sbc side. when a wake-up is detected by the sbc (can, wake-up input, forced wake-up, etc.), the sbc turns itself into normal request mode and activates the vdd1 main regulator. when the main regulator is fully active, then the wake-up is signalled to the mcu through the int pin. the int pin is pulled low for 10 s and then returns high. wake-up events can be read through the spi registers. stop mode: wake-up from mcu side when the application is in st op mode, the wake-up event may come to the mcu. in this case, the mcu has to signal to the sbc that it has to go into normal mode in order for the vdd1 regulator to be able to deliver full current capability. this is done by a low to high transition of the cs pin. the cs pin low to high activation has to be done as soon as possible after the mcu. the sbc generates a pulse at the int pin. alternatively the l0 and l1 inputs can also be used as wake- up from the stop mode. stop mode current monitoring if the current in stop mode exceeds the i dd1s-wu threshold, the sbc jumps into normal request mode, activates the vdd1 main regulator, and generates an interrupt to the mcu. this interrupt is not maskable and a not bit are set into the int register. software watchdog in stop mode if the watchdog is enabled (r egister mcr, bit wdstop set), the mcu has to wake-up independently of the sbc before the end of the sbc watchdog time. in order to do this, the mcu has to signal the wake-up to the sbc through the spi wake-up ( cs pin low to high transition to activated the spi wake-up). then the sbc wakes up and jumps into the normal request mode. the mcu has to configure the sbc to go to either into normal or standby mode. the mcu can then choose to go back into stop mode. if no mcu wake-up occurs within the watchdog timing, the sbc will activate the reset pin and jump into the normal request mode. the mcu can then be initialized.
analog integrated circuit device data freescale semiconductor 27 33889 functional device operation operational modes normal request mode this is a temporary mode automatically accessed by the device after a wake-up event from sleep or stop mode, or after device power up. in this mode, the vdd1 regulator is on, v2 is off, and the reset pin is high. as soon as the device enters the normal request mode, an internal 350 ms timer is started. during these 350 ms, the microcontroller of the application must address the sbc via the spi and configure the watchdog register (tim1 regist er). this is the condition for the sbc to leave the normal request mode and enter the normal mode, and to set the watchdog timer according to the configuration done during the normal request mode. the ?batfail flag? is a bit which is triggered when v sup falls below 3.0 v. this bit is set into the mcr register. it is reset by the mcr register read. internal clock this device has an internal clock used to generate all timings (reset, watchdog, cyclic wake-up, filtering time etc....). reset pin a reset output is available in order to reset the microcontroller. reset causes are: ?v dd1 falling out of range: if v dd1 falls below the reset threshold (parameter r st-th ), the reset pin is pulled low until v dd1 returns to the nominal voltage. ? power on reset: at device power on or at device wake-up from sleep mode, the reset is maintained low until v dd1 is within its operation range. ? watchdog timeout: if the watc hdog is not cleared, the sbc will pull the reset pin low for the duration of the reset duration time ( parameter: reset-dur). for debug purposes at 25c, t he reset pin can be shorted to 5.0 v. software watchdog ( selectable window or timeout watchdog) the software watchdog is used in the sbc normal and stand-by modes for monitoring the mcu. the watchdog can be either a window or timeout. this is selectable by the spi (register tim, bit wdw). defa ult is the window watchdog. the period of the watchdog is selectable by the spi from 5.0 to 350 ms (register tim, bits wdt0 and wdt1). when the window watchdog is selected, the closed window is the first half of the selected period, and the open window is the second half of the period. the watchdog can only be cleared within the open window time. an attempt to clear the watchdog in the closed window will generate a reset. the watchdog is cleared through the spi by addressing the tim register. refer to ?table for reset pin operations? operation in mode 2. wake-up capabilities several wake-up capabilities are available for the device when it is in sleep or stop mode. when a wake-up has occurred, the wake-up event is stored into the wur or can registers. the mcu can then access the wake-up source. the wake-up options are selectable through the spi while the device is in normal or standby mode, and prior to entering low power mode (sleep or stop mode). wake-up from wake-up in puts (l0, l1) without cyclic sense the wake-up lines are dedicated to sense external switch states, and when changes occur to wake-up the mcu (in sleep or stop modes). the wake-up pins are able to handle 40 v dc. the internal threshold is 3.0 v typical, and these inputs can be used as an input port expander. the wake-up inputs state can be read through the spi (register wur). l0 has a lower threshold than l1 in order to allow a connection and wake-up from a digital output such as a can physical interface. cyclic sense wake-up (cyclic sense timer and wake-up inputs l0, l1) the sbc can wake-up from a state change of one of the wake-up input lines (l0, l1), while the external pullup or pulldown resistor of the switc hes associated to the wake-up input lines are biased with hs 1 vsup switch. the hs1 switch is activated in sleep or stop mode from an internal timer. cyclic sense and forced wake-up are exclusive. if cyclic sense is enabled, the forced wake-up can not be enabled. info for cyclic sense + dual edge selection in case the cyclic sense and lx both level sensitive conditions are use together, the initial value for lx inputs are sampled in two cases: 1) when the register lpc[d3 and d0] are set and 2) at cyclic sense event, that is when device is in sleep or stop mode and hs1 is active. the consequence is that when the device wake up by lx transition, the new value is sampled as default, then when the device is set back into low power again, it will automatically wake up. the user should reset the lpc bits [d3 and d0] to 0 and set them again to the desired value prior to enter sleep or stop mode. forced wake-up the sbc can wake-up automatically after a predetermined time spent in sleep or stop mode. forced wake-up is enabled by setting bit fwu in the lpc register. cyclic sense and forced wake-up are exclusive. if forced wake-up is enabled, the cyclic sense can not be enabled.
analog integrated circuit device data 28 freescale semiconductor 33889 functional device operation operational modes can wake-up the device can wake-up from a can message. a can wake-up cannot be disabled. spi wake-up the device can wake-up by the cs pin in sleep or stop mode. wake-up is detected by the cs pin transition from a low to high level. in stop mode this correspond to the condition where the mcu and sbc are both in stop mode, and when the application wake-up events come through the mcu. system power up at power up the device automatically wakes up. device power up, sbc wake up after device or system power up or a wake-up from sleep mode, the sbc enters into ?reset mode? then into ?normal request mode?. battery fall early warning this function provides an interrupt when the vsup voltage is below the 6.1 v typical. this interrupt is maskable. a hysteresis is included. operation is only in normal and stand-by modes. vbat low state reports in the ior register. reset and wdog operation the following figure shows the reset and watchdog output operations. reset is active at device power up and wake-up. reset is activated in case the vdd1 falls or the watchdog is not triggered. the wdog output is active low as soon as the reset goes low and stays low for as long as the watchdog is not properly re-activated by the spi. the wdog output pin is a push pull structure than can drive external components of the application, for instance to signal the mcu is in a wrong oper ation. even if it is internally turned on (low-state), the reset pin can be forced to 5.0 v at 25c only, thanks to its inte rnally limited current drive capability. the wdog stays low until the watchdog register is properly addressed through the spi. figure 10. reset and wdog function diagram debug mode application hardware and software debug with the sbc. when the sbc is mounted on the same printed circuit board as the micro controller, it supplies both application software and the sbc with a dedicated routine that must be debugged. the following features allow the user to debug the software by disabling the sbc internal software watchdog timer. device power up, reset pin connected to vdd1 at sbc power up, the vdd1 voltage is provided, but if no spi communication occurs to configure the device, a reset occurs every 350 ms. in order to allow software debugging and avoid an mcu reset, the reset pin can be connected directly to vdd1 by a jumper. debug modes with software watchdog disabled though spi (normal debug, standby debug and stop debug) the software watchdog can be disabled through the spi. in order to avoid unwanted watchdog disables, and to limit the risk of disabling the watchdog during an sbc normal operation, the watchdog disable has to be performed with the following sequence: step 1) power down the sbc step 2) power up the sbc (the batfail bit is set, and the sbc enters normal request mode) step 3) write to the tim1 regist er to allow the sbc to enter normal mode step 4) write to the mcr register with data 0000 (this enables the debug mode). (complete spi byte: 000 1 0000) reset wdog vdd1 spi spi cs watchdog timeout watchdog register addressed watchdog period w/d clear
analog integrated circuit device data freescale semiconductor 29 33889 functional device operation operational modes step 5) write to the mcr register normal debug (0001 x101), stand-by debug (0001 x110), or stop debug (0001 x111) while in debug mode, the sbc can be used without having to clear the w/d on a regular basis to facilitate software and hardware debugging. step 6) to leave the debug mode, write 0000 to the mcr register. to avoid entering the debug mode after a power up, first read the batfail bit (mcr read) and write 0000 into the mcr. figure 11 illustrates entering the debug mode. figure 11. debug mode enter mcu flash programmi ng configuration to facilitate the possibility of down loading software into the application memory (mcu eeprom or flash), the sbc allows the following capabilities: the vdd1 can be forced by an external power supply to 5.0 v and the reset and w dog output by external signal sources to zero or 5.0 v without damage. this supplies the co mplete application board with external power supply and applies the correct signal to the reset pin. vsup spi mcr(step4) batfail vdd1 debug mode mcr (step5) spi: read batfail mcr (step6) sbc in debug mode, no w/d sbc not in debug mode and w/d on tim1(step 3)
analog integrated circuit device data 30 freescale semiconductor 33889 functional device operation operational modes can transceiver description figure 12. simplified block diagram of the can transceiver of the mc33889 general description can driver: the canh driver is a ?high side? switch to t he v2 voltage (5v). the canl driver is a ?low side? switch to gnd.the turn on and turn off time is controlled in order to control the slew rate, and the canh and canl driver have a current limitation as well as an over temperature shutdown. the can h or canl driver can be disabled in case a failure is detected on the can bus (ex: canh driver is disabled in case canh is shorted to v dd ). the disabling of one of the drivers is contro lled by the can logic and the communication continues via the other drivers. when the failure is removed the logic detects a failure recovery and automatically reenables the associated driver. the can drivers are also disabled in case of a tx failure detection. bus termination: the bus is terminated by pull up and pull down resistors, which are connected to gnd, vdd or vbat through dedicated rtl and rth pins and internal switches srh, srl, stvbat. each node must have a resistor connected between canh and rth and between canl and rtl. the resistor value should be between 500 and 16000 ohms. transmitter function can bus levels are called dominant and recessive, and correspond respectively to low and high states of the tx input pin. dominant state: the canh and canl drivers ar e on. the voltage at canl is <1.4v, the voltage at canh is >3.6v, and the differential voltage between canh and canl line is >2.2v (3.6v-1.4v). recessive state: this is a weak state, wher e the canh and canl drivers are off. the canl line is pulled up to 5v via the rtl pin and rtl resistor, and the canh line is pull down via the rth and rth resistor. the resultant voltage at canl is 5v and 0v at canh. the differential voltage is -5v (0v - 5v). the recessive state can be over wr itten by any other node forcing a dominant state. gnd canh v2 rtl canl rth vdiff sh sl rxd stvbat srl srh driver driver txd vse-h (1.85v) vse-l (3.05v) canh canl failure detection rx multiplexer tx driver hwake lwake vwake-h (2v) vwake-l (3v) canh canl can spi vsup icanlpu icanhpd mode control v2 rtl rth v2
analog integrated circuit device data freescale semiconductor 31 33889 functional device operation operational modes receiver function in normal operation (no bus failures), rx is the image of the differential bus voltage. the differential receiver inputs are connected to canh and canl. the device incorporates single ended comparators connected to canh and canl in order to monitor the bus state as well as detect bus failures. failures are reported via the spi. in normal operation when no failure is present, the differential comparator is active . under a fault condition, one of the two canh or canl pins can be become non- operational. the single ended comparator of either canh or canl is activated and continues to report a bus state to rx pin. the device permanently monitors the bus failure and recovery, and as soon as fault disappears, it automatically switches back to differential operation. can interface operation mode the can has 3 operation modes: txrx (transmit- receive), receive only, an d term-vbat (terminated to vbat). the mode is selected by the spi. as soon as the mc33889 mode is sleep or stop (selected via mcr register), the can interface automatic ally enters tem-vbat mode. tx rx mode: in this mode, the can drivers and receivers are enabled, and the device is able to send and receive messages. bus failures are detected and managed, this means that in case of a bus failure, one of the can drivers can be disabled, but communication continues via the remaining drivers. receive only mode: in this mode, the transmitter path is disabled, so the device does not drive the bus. it maintains canl and canh in the recessive state. the receiver function operates normally. termvbat mode: in this mode, the transmitte r and receiver functions are disabled. the canl pin is connected to v sup through the rtl resistor and internal pull up resistor of 12.5kohms. in this mode, the device monitors the bus activity and if a wake up conditions is encountered on the can bus, it will wakes up the mc33889. the device will enter into a normal request mode if low power mode was in sleep, or gener ates an int. it enters into normal request mode if low power mode was in stop mode. if the device was in normal or stand by mode, the rx pin will report a wake up (feature no t available on the mc33889b). see rx pin behavior. bus failure detection general description: the device permanently monitors the bus lines and detects faults in normal and receive only modes. when a fault is detected, the device auto matically takes appropriate actions to minimize the system current consumption and to allow communication on the network. depending on the type of fault, the mode of operation, and the fault detected, the device automatically switches off one or more of the following functions: canl or canh line dr iver, rtl or rth termination resistors, or internal switches . these actions are detailed in the following table. the device permanently monitors the faults and in case of fault recovery, it automatically switches back to normal operation and reconnects the op en functions. fault detection and recovery circuitry have internal filters and delays timing, detailed in the ac characteristics parameters. the failure list identification and the consequence on the device operation are described in following table. the failure detection, and recovery principl e, the transceiver state after a failure detected, timing for failure detection and recovery can be found in the iso11898-3 standard. the following table is a summary of the failure identifications and of the c onsequences on the can driver and receiver when the can is in tx rx mode.
analog integrated circuit device data 32 freescale semiconductor 33889 functional device operation operational modes open wire detection operation: description: the canh and canl open wire failures are not described in the iso document. open wire is only diagnostic information, as no can driver or receiver state will change in case of an open wire condition. in case one of the can wires are open, the communication will continue through the remaining wire. in this situation the mc33889 will receive information on one wire only and the consequences are as follows: when the bus is set in dominant: - the differential receiver will toggle - only one of the single ended receivers canh or of canl will toggle the following figure illustrates the can signal during normal communication and in the example of a canh open wire. the single ended receiver is sampled at the differential receiver switching event, in a window of 1 s. bus failure identification description consequence on can driver consequence on rx pin no failure default operation: can h and canl driver active, rth and rtl termination switched on default operation: report differential receiver output 1 canh open wire default operation default operation 5 canh shorted to gnd default operation default operation 8, 3a canh shorted to vdd (5v) canh driver turn off. rth termination switched off rx report canl single ended receiver 3 canh shorted to vbat canh driver turn off. rth termination switched off rx report canl single ended receiver 2 canl open wire default operation default operation 4, 7 canl shorted to gnd or canl shorted to canh canl driver is off. rtl termination switched off rx report canh single ended receiver 9 canl shorted to vdd (5v) canl driver is on. rtl termination active default operation 6 canl shorted to vbat canl driver is off. rtl termination switched off rx report canh single ended receiver
analog integrated circuit device data freescale semiconductor 33 33889 functional device operation operational modes figure 13. can normal signal communication an d can open wire figure 14. open wire detection principle open wire detection, mc33889b and d: failure detection: the device will detect a difference in toggling counts between the differential receiver and one of the single ended receivers. every time a difference in count is detected a counter is incremented. when the counter reaches 4, the device detects and reports an open wire condition. the open wire detection is performed only when the device receives a message and not when it send message. open wire recovery: when the open wire failure has recovered, the difference in count is reduced and the device detects the open wire recovery. mc33889b: when detection is complete, the counter is no longer incremented. it can only be decremented by sampling of the dominant level on the s-h (s-l) (recovery pulse). when it reaches zero, the failure has recovered. canh canl diff s-l s-h -3.2v rec dom rec sampling point canh canl diff s-l s-h -3.2v rec dom rec sampling point sampling recessive level = > open wire ?detection pulse? 1us (no open wire, or open wire recovery) (can h open wire) sampling dominant level = > no failure or ?recovery pulse? diff canh canl s-h 1us sampling dom rec s-l 1us sampling canh counter l-open l-counter +/- (count = 4) recover (count = 0)
analog integrated circuit device data 34 freescale semiconductor 33889 functional device operation operational modes in application, with can co mmunication, a recovery condition is detected after 4 a cknowledge bits are sent by the mc33889b. mc33889d: when detection is complete , the counter is decremented by sampling the dominant pulse (recovery pulse) on s-h (s- l), and incremented (up to 4) by sampling the recessive pulse (detection pulses) on s-h (s-l). it is necessary to get 4 consecutive dominant samples (recovery pulse) to get to zero. when reaching zero, the failure is recovered. in application with real can communication, a recovery condition will not be detected by a single acknowledge bit send by mc33889d, but requires a complete can message (at least 4 dominant bits) send in dual wire mode, without reception of any bit in single wire mode. tx permanent dominant detection: in addition to the previous list, the mc33889 detects a permanent low state at the tx input which results in a permanent dominant bus state. if tx is low for more than 0.75-4ms, the bus output driver is disabled. this avoids blocking communication between other nodes of the network. txd is reported via the spi (rcr register bit d1: txfailure). tx permanent dominant recovery is done with tx recessive for more than typ 32us. rx pin behavior while can interface is in termvbat. the mc33889d is able to signal bus activity on rx while the can interface is in termvbat and the sbc in normal or standby mode. when the bus is driven into a dominant state by another sending node, each dominant state is reported at rx by a low level, after a delay of t wake . the bus state report is done through the can interface wake up comparator on canl and canh, and thus operates also in case of bus failure. this is illustrated in the following figure.
analog integrated circuit device data freescale semiconductor 35 33889 functional device operation operational modes figure 15. bus state report of the can in terface wake-up comparator on canl and canh rx canl canh dominant recessive state state canl terminated to vbat dominant recessive state state other can node send t wake t wake can in txrx mc33889d in normal mode can in termvbat mc33889d in normal mode, standby mode or in stop mode can in txrx mc33889d in normal mode dominant state t wake tx sender node rx mc33889d trx_dom tbus_dom t wake : duration of the can wake up filter, typ 16 s. the mc33889d rx dominant low level duration is the difference between the duration of the bus minus the twake, as illustrated below (trx_dom = tbus_dom - twake) example: a dominant duratio n at the bus level of 5 bits of 8us each results in a 40us bus dominant. this results in a 24 s (40 s-16 s) dominant level at rx of mc33889d (while the can of the mc33889d is in termvbat). tx mc33889d
analog integrated circuit device data 36 freescale semiconductor 33889 functional device operation operational modes the following table summarizes the device behavior when a can wake up event occurs. gnd shift detection general when normally working in tw o-wire operating mode, the can transmission can afford some ground shift between different nodes without trouble. should a bus failure occur, the transceiver switches to si ngle-wire operation, therefore working with less noise margin. the affordable ground shift is decreased. the sbc provides a ground sh ift detection for diagnosis purpose. the four ground shift levels are selectable and the detection is stored in the ior re gister which is accessible via the spi. detection principle the gnd shift to detect is selected via the spi from 4 different values (-0.3 v, -0.7 v, -1.2 v, -1.7 v). at each tx falling edge (end of recessive state), the canh voltage is sensed. if it is detected to be below the selected gnd shift threshold, the bit shift is set at 1 in the ior regi ster. no filter is implemented. required filtering for reliable detection should be done by software (e.g. several trials). device state description table 6. summary of rx pin operations for wake up signaling sbc mode can state mc33889b mc33889d normal te r m v b a t no event on rx, no bit set rx pulse (1), bit canwu is not set standby te r m v b a t no event on rx, no bit set rx pulse (1), bit canwu is not set sleep te r m v b a t sbc mode transition to normal request, bit canwu set sbc mode transition to normal request, bit canwu set stop te r m v b a t int pulse, bit canwu set int pulse, bit canwu set notes 29. pulse duration is bus dominant duration minus twake. table 7. 33889 table of operations the table below describe the sbc operation modes. mode voltage regulator hs1 switch wake-up capabilities (if enabled) reset pin int software watchdog can cell normal request vdd1: on v2: off hs1: off low for 1ms, then high term vbat normal vdd1: on v2: on hs1 controllable normally high. active low if w/d or vdd1 under voltage occur if enabled, signal failure (vdd pre warning temp, can, hs1) running term vbat tx/rx rec only standby vdd1: on v2: off hs1 controllable normally high. active low if w/d or vdd1 under voltage occur if enabled, signal failure (vdd temp, hs1) running term vbat tx/rx rec only stop vdd1: on (limited current capability) v2: off hs1: off or cyclic can (always enable) spi and l0,l1 cyclic sense or forced wake-up normally high. active low if w/d or vdd1 under voltage occur signal sbc wake-up (not maskable) - running if enabled - not running if disabled term vbat.
analog integrated circuit device data freescale semiconductor 37 33889 functional device operation operational modes figure 16. simplified state machine sleep vdd1: off v2: off hs1 off or cyclic can (always enable spi and l0,l1 cyclic sense forced wake-up low not active no running term vbat. table 7. 33889 table of operations the table below describe the sbc operation modes. mode voltage regulator hs1 switch wake-up capabilities (if enabled) reset pin int software watchdog can cell state machine (not valid in debug modes) power down reset normal request standby stop normal sleep reset counter (1 ms) expired sbc power up vdd1 low or w/d: time out 350 ms & !nostop 1 wake-up spi: standby & w/d trigger (note1) 3 spi: standby spi: normal spi: stop & cs low to high transition spi: st op & cs low to h i g h t r ansiti o n w/d: trigge r 4 2 w/d: timeout or vdd1 low nostop & spi: sleep & cs low to high transition nostop & spi: sleep & cs low to high transition w/d: timeout & nostop & !batfail 1 w/d: timeout or vdd1 low 1 2 w / d : t i m e o u t o r v d d 1 l o w ( n o t e 2 ) 1 wake-up (vdd1 high temperature or (vddd1 low > 100 ms & vsup >bfew)) & nostop & !batfail 1 2 3 4 denotes priority state machine description: ?nostop? means nostop bit = 1 ?! nostop? means nostop bit = 0 ?batfail? means batfail bit = 1 ?! batfail? means batfail bit = 0 ?vdd1 over temperature? means vdd1 thermal shutdown occurs ?vdd1 low? means vdd1 below reset threshold ?vdd1 low > 100 ms? means vdd1 below reset threshold for more than 100 ms ?w/d: trigger? means tim1 register write operation. vsup > bfew means vsup > battery fall early warning (6.1 v typical) ?w/d: timeout? means tim1 register not written before w/d timeout period expired, or w/d written in incorrect time window if window w/d selected (except stop mode). in normal request mode timeout is 355 ms p2.2 (350 ms p3)ms. ?spi: sleep? means spi write command to mcr register, data sleep ?spi: stop? means spi write command to mcr register, data stop ?spi: normal? means spi write command to mcr register, data normal ?spi: standby? means spi write command to mcr register, data standby note 1: these 2 spi commands must be send in this sequence and consecutively. note 2: if w/d activated
analog integrated circuit device data 38 freescale semiconductor 33889 functional device operation operational modes figure 17. behavior at sbc power up figure 18. transitions to enter debug modes behavior at sbc power up transitions to enter debug modes normal request standby debug spi: mcr (0000) & normal debug normal w / d : t r i g g e r reset reset counter (1.0 ms) expired w/d: timeout 350 ms normal debug spi: mcr (0000) & standby debug power down
analog integrated circuit device data freescale semiconductor 39 33889 functional device operation operational modes figure 19. simplified state machine in debug mode simplified state machine in debug modes spi: standby & w/d: trigger wake-up normal request standby debug spi: normal debug normal w / d : t r i g g e r standby spi: standby debug spi: standby debug s p i : n o r ma l d e b u g reset reset counter (1ms) expired w/d: timeout 350ms sleep & !batfailnostop & spi: sleep spi: normal debug normal debug spi : st a ndby d e bug stop (1) spi: stop e e wake-up r r r r r r r (1) if stop mode entered, it is entered without watchdog, no matter the wdstop bit. (e) debug mode entry point (step 5 of the debug mode entering sequence). (r) represents transitions to reset mode due to vdd1 low.
analog integrated circuit device data 40 freescale semiconductor 33889 functional device operation logic commands and registers logic commands and registers spi interface figure 20. data format description the spi is a 8 bit spi. first 3 bits are used to identify the internal sbc register addr ess, bit 4 is a read/write bit. the las t 4 bits are data send from mcu to sbc or read back from sbc to mcu. during write operation state of miso has no signification. during read operation only the last 4 bits at miso have a meaning (content of the accessed register) following tables describe the spi regi ster list, and register bit meaning. registers ?reset value? is also described, as well as the ?res et condition?. reset condition is the condition which cause the b it to be set at the ?reset value?. possible reset condition are: power on reset: por sbc mode transition: nr2r - normal request to reset mode nr2n - normal request to normal mode n2r - normal to reset mode stb2r - standby to reset mode sto2r - stop to reset mode sbc mode: reset - sbc in reset mode mosi miso bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 d0 d1 d2 d3 r/w a0 a1 a2 data address read operation: r/w bit = 0 write operation: r/w bit = 1
analog integrated circuit device data freescale semiconductor 41 33889 functional device operation logic commands and registers table 8. list of registers register description table 9. mcr register table 10. control bits name address description comment and usage mcr $0 0 0 mode control register write: control of normal, st andby, sleep, and stop modes read: batfail flag and other status bits and flags rcr $0 0 1 reset control register write: configuration of reset volta ge level, wd in stop mode, low power mode selection read: can wake-up event, tx permanent dominant can $0 1 0 can control register write: can module control: tx/r x, rec only, term vbat, normal and extended modes, filter at l0 input. read: can failure status bits ior $0 1 1 i/o control register write: hs1 (high-side switch) control in normal and standby mode. gnd shift register level selection read: hs1 over temp bit, shift bit (gnd shift above selection), v sup below 6.1v, v2 below 4.0 v wur $1 0 0 wake-up input register write: control of wake-up input polarity read: wake-up input, and re al time lx input state tim $1 0 1 timing register write: tim1, watchdog timing control, window or timeout mode. write: tim2, cyclic sense and force wake-up timing selection lpc $1 1 0 low power mode control register write: hs1 periodic activation in sleep and stop modes force wake-up control intr $1 1 1 interrupt register write: interrupt source configuration read: int source mcr d3 d2 d1 d0 $000b w mctr2 mctr1 mctr0 r batfail vddtemp gfail wdrst reset 0 0 0 0 reset condition por, reset por, reset por, reset mctr2 mctr1 mctr0 sbc mode description 0 0 0 enter/leave debug mode to enter debug mode, sbc must be in normal or standby mode and batfail (1) must be still at 1. to leave debug mode, batfail must be at 0. 0 0 1 normal 0 1 0 standby 0 1 1 stop, watchdog off (2)
analog integrated circuit device data 42 freescale semiconductor 33889 functional device operation logic commands and registers (1): bit batfail cannot be set by spi. batfail is set when v sup falls below 3v. (2): watchdog on or off depends on the rcr register bit d3. (3): before entering sleep mode, bit nostop in rcr register must be previously set to 1. (4): stop command should be replaced by stop watchdog off. mctr2=0, mctr1= mctr0=1 table 11. status bits table 12. rcr register 0 1 1 stop, watchdog on (2) 1 0 0 sleep (3) 1 0 1 normal no watchdog running, debug mode 1 1 0 standby 1 1 1 stop (4) status bit description gfail logic or of can failure, hs1 failure, v2low batfail battery fail flag (v sup <3v) vddtemp temperature pre-warn ing on vdd (latched) wdrst watchdog reset occurred rcr d3 d2 d1 d0 $001b w wdstop nostop rstth r txfailure canwu reset 1 0 0 reset condition por, reset por, nr2n por mctr2 mctr1 mctr0 sbc mode description
analog integrated circuit device data freescale semiconductor 43 33889 functional device operation logic commands and registers table 13. control bits table 14. can register some description. status bit bit value description wdstop 0 no watchdog in stop mode 1 watchdog runs in stop mode nostop 0 stop mode is default low power mode 1 sleep mode is default low power mode rstth 0 reset threshold 1 selected (typ 4.6v) 1 reset threshold 2 selected (typ 4.2v) canwu 1 wake-rom can txfailure 1 tx permanent dominant (can) can d3 d2 d1 d0 $010b w fdis cext cctr1 cctr0 r cs3 cs2 cs1 cs0 reset 0 0 0 0 reset condition por, can por, can por, can por, can
analog integrated circuit device data 44 freescale semiconductor 33889 functional device operation logic commands and registers fault tolerant can trans ceiver standard modes the can transceiver standard mode can be programmed by setti ng cext to 0. the transceiver cell will then be behave as known from mc33388. table 15. can transceiver modes table 16. can transceiver extended modes (can with cext bit =1 is not recommended) fault tolerant can transceiver extended modes by setting cext to 1 the transceiver cell supports sub bus communication note1: cext bit should be set at 0. the ca n operation in extended mode is not recommended. note: if dfis bit is set to 1, wur regist er must be read before going into sleep or stop mode in order to clear the wake-up fla g. during read out l0 must be at high level and should stay high when entering sleep or stop. cext cctr1 cctr0 mode 0 0 0 termvbat 0 0 1 0 1 0 rxonly 0 1 1 rxtx cext (1) cctr1 cctr0 mode 1 0 0 termvbat 1 0 1 termvdd 1 1 0 rxonly 1 1 1 rxtx fdis l0 wake input filter (20 s typical) 0 enable (lo wake threshold selectable by wur register) 1 disable (l0 wake-up threshold is low level only, no matter d0 and d1 bits set in wur register).
analog integrated circuit device data freescale semiconductor 45 33889 functional device operation logic commands and registers table 17. status bits comments: cs2 bit at 0 = open failure. cs2 bit at 1 = short failure. (cs3 bit at 0 and (cs1 = 1 or cs2 =1)) = canh failure. cs3 bit at 1 = canl failure. cs1 and cs0 bits: short type fail ure coding (gnd, vdd or vbat). in case of multiple failures, the last failure is reported. cs3 cs2 cs1 cs0 bus failure # description 0 0 0 0 no failure 0 0 0 1 1 canh open wire 0 1 0 1 5 canh short circuit to ground 0 1 1 0 8, 3a vdd 0 1 1 1 3 vbat 1 0 0 1 2 canl open wire 1 1 0 1 4, 7 canl short circuit to ground / canh 1 1 1 0 9 vdd 1 1 1 1 6 vbat
analog integrated circuit device data 46 freescale semiconductor 33889 functional device operation logic commands and registers table 18. ior register. table 19. control bits table 20. gnd shift selection ior d3 d2 d1 d0 $011b w hs1on gslr1 gslr0 r shift hs1ot v2low vsuplow reset 0 0 0 reset condition por, reset por, reset por, reset hs1on hs1 0 hs1 switch turn off 1 hs1 switch turn on gslr1 gslr0 typical gnd shift comparator level 0 0 -0.3 v 0 1 -0.7 v 1 0 -1.2 v 1 1 -1.7 v shift state 0 gnd shift value is lower than the level selected by the gslr1 and gslr2 bit 1 gnd shift value is higher than the level selected by the gslr1 and gslr2 bit
analog integrated circuit device data freescale semiconductor 47 33889 functional device operation logic commands and registers table 21. status bits (*) once the hs1 switch has been turned off because of over temperature, it can be turned on again by setting the appropriate control bit to ?1?. wur register the local wake-up inputs l0 and l1 can be used in both norm al and standby mode as port expander and for waking up the sbc in sleep or stop mode. table 22. wur register table 23. control bits:. status bit description hs1ot (*) high-side 1 over temperature shift gnd shift level selected by gslr1 and gslr2 bits is reached v2low v2 below 4.0 v typical vsuplow v sup below 6.1 v typical wur d3 d2 d1 d0 $100b w lctr3 lctr2 lctr1 lctr0 r l1wub l1wua l0wub l0wua reset 1 1 1 1 reset condition por, nr2r, n2r, stb2r, sto2r lctr3 lctr2 lctr1 lctr0 l0 configuration l1 configuration x x 0 0 inputs disabled x x 0 1 high level sensitive x x 1 0 low level sensitive x x 1 1 both level sensitive 0 0 x x inputs disabled 0 1 x x high level sensitive 1 0 x x low level sensitive 1 1 x x both level sensitive
analog integrated circuit device data 48 freescale semiconductor 33889 functional device operation logic commands and registers table 24. status bits tim registers description: this register is split in to 2 sub registers, tim1 and tim2. tim1 controls the watchdog timing selection as well as the wi ndow or timeout option. tim1 is selected when bit d3 is 0. tim2 is used to define the timing for the cyclic sense and forc ed wake-up function. tim2 is selected when bit d3 is 1. no read operation is allowed for registers tim1 and tim2 tim register table 25. tim register. l0wub l0wua fdis bit in can register description 0 0 0 no wake-up occurred at l0 (sleep or stop mode). low level state on l0 (standby or normal mode) 1 1 0 wake-up occurred at l0 (sleep or stop mode). high level state on l0 (standby or normal mode) 0 1 1 wake-up occurred at l0 (sleep or stop mode with l0 filter disable). wur must be set to xx00 before sleep or stop mode. l1wub l1wua description 0 0 no wake-up occurred at l1 (sleep or stop mode). low level state on l1 (standby or normal mode) 1 1 wake-up occurred at l1 (sleep or stop mode). high level state on l1 (standby or normal mode) tim1 d3 d2 d1 d0 $101b w 0 wdw wdt1 wdt0 r reset 0 0 0 reset condition por, reset por, reset por, reset
analog integrated circuit device data freescale semiconductor 49 33889 functional device operation logic commands and registers table 26. watch dog table 27. jwatchdog operation (window and timeout) tim2 register the purpose of tim2 register is to select an appropriate timing for sensing the wake-up circuitry or cyclically supplying devic es by switching on or off hs1 table 28. tim2 register wdw wdt1 wdt0 watchdog timing [ms] 0 0 0 10 no window watchdog 0 0 1 50 0 1 0 100 0 1 1 350 1 0 0 10 window watchdog enabled (window lenght is half the watchdog timing) 1 0 1 50 1 1 0 100 1 1 1 350 window closed window open wd timing * 50% wd timing * 50% watchdog period for watchdog clear no watchdog clear window open watchdog period for watchdog clear (wd timing selected by tim 1 bit wdw=1) (wd timing selected by tim 1, bit wdw=0) timeout watchdog window watchdog tim2 d3 d2 d1 d0 $101b w 1 csp2 csp1 csp0 r reset 0 0 0 reset condition por, reset por, reset por, reset
analog integrated circuit device data 50 freescale semiconductor 33889 functional device operation logic commands and registers table 29. cyclic sense timing lpc register description: this register controls: - the state of hs1 in stop and sleep m ode (hs1 permanently off or hs1 cyclic) - enable or disable the forced wake-up function (sbc automatic wake-up after time spend in sleep or stop mode, time defined by tim2 register) - enable or disable the sense of the wake-up inputs (lx) at sampling point of the cyclic sense period (lx2hs1 bit). table 30. lpc register csp2 csp1 csp0 cyclic sense timing [ms] 0 0 0 5 0 0 1 10 0 1 0 20 0 1 1 40 1 0 0 75 1 0 1 100 1 1 0 200 1 1 1 400 cyclic sense timing cyclic sense on time t hs1 sample 10 s to 20 s lpc d3 d2 d1 d0 $110b w lx2hs1 fwu idds hs1auto r reset 0 0 0 0 reset condition por, nr2r, n2r, stb2r, sto2r por, nr2r, n2r, stb2r, sto2r por, nr2r, n2r, stb2r, sto2r por, nr2r, n2r, stb2r, sto2r
analog integrated circuit device data freescale semiconductor 51 33889 functional device operation logic commands and registers table 31. intr register table 32. control bits: when the mask bit has been set, int pin goes low if the appropriate condition occurs. lx2hs1 hs1auto wake-up inputs supplied by hs1 autotiming hs1 x 0 off x 1 on, hs1 cyclic, period defined in tim2 register 0 x no 1 x yes, lx inputs sensed at sampling point bit description fwu if this bit is set, and the sbc is turned into sleep or stop mode, the sbc wakes up after the time selected in the tim2 register idds bit = 0: i dds-wu1 selected (lowest value, typ 3.5ma) bit = 1: i dds-wu2 selected (highest value, typ 14ma) intr d3 d2 d1 d0 $111b w vsuplow hs1ot-v2low vddtemp canf r vsuplow hs1ot vddtemp canf reset 0 0 0 0 reset condition por, reset por, reset por, reset por, reset control bit description canf mask bit for can failures (or of any can failure) vddtemp mask bit for vdd medium temperature hs1ot-v2low mask bit for hs1 over temperature or v2 below 4v vsuplow mask bit for sup below 6.1v
analog integrated circuit device data 52 freescale semiconductor 33889 functional device operation logic commands and registers table 33. status bits: notes: if hs1ot-v2low interrupt is on ly selected (only bit d2 set in intr register), reading intr register bit d2 leads to two possibilities: bit d2 = 1: int source is hs1ot bit d2 = 0: int source is v2low. upon a wake-up condition from stop mode due to over current detection (i dd1s-wu1 or i dd1s-wu2 ), an int pulse is generated, however intr register contain remains at 0000 (not bit set into the intr register). status bit description canf can failure vddtemp vdd medium temperature hs1ot hs1 over temperature vsuplow v sup below 6.1v typical
analog integrated circuit device data freescale semiconductor 53 33889 typical applications typical applications figure 21. 33889d/33889b simplified typical application with ballast transistor figure 22. 33889d/33889b simplified typi cal application without ballast transistor programmable spi interface dual voltage regulator vsup monitor vdd1 monitor hs1 control mode control reset watchdog wake-up input cs sclk mosi r eset int v2ctrl vdd1 hs1 oscillator v2 wdog vsup v2 interrupt vbat q1 l0 l1 miso rxd txd low speed physical interface canl canh rrth rth rtl rrtl fault tolerant can gnd 5v/200ma can supply 5v 5v/200ma rb programmable spi interface dual voltage regulator vsup monitor vdd1 monitor hs1 control mode control reset watchdog wake-up input cs sclk mosi reset int 5v/200ma v2ctrl (open) vdd1 hs1 oscillator v2 wdog vsup v2 interrupt vbat l0 l1 miso rx tx low speed physical interface canl canh rrth rth rtl rrtl fault tolerant can gnd can supply 5v/100ma 5v/100ma
analog integrated circuit device data 54 freescale semiconductor 33889 packaging package dimensions packaging package dimensions important for the most current revision of the package, visit www.freescale.com and do a keyword search on the 98a number listed below. dw suffix eg suffix (pb-free) 28-pin plastic package 98asb42345b issue g
analog integrated circuit device data freescale semiconductor 55 33889 packaging package dimensions dw suffix eg suffix (pb-free) 28-pin plastic package 98asb42345b issue g
analog integrated circuit device data 56 freescale semiconductor 33889 additional documentation thermal addendum (rev 2.0) additional documentation thermal addendum (rev 2.0) introduction this thermal addendum is provided as a supplement to the mc33889 technical datasheet. the addendum pr ovides thermal performance information that may be critical in the design and development of system appl ications. all electrical, application, and packaging information is provided in the datasheet. packaging and thermal considerations the mc33889 is offered in a 28 pin soicw, single die package. there is a single heat source (p), a single junction temperature (t j ), and thermal resistance (r ja ). the stated values are solely for a thermal performance comparison of one package to another in a standardized environment. this methodology is not meant to and will not predict the perfor mance of a package in an application- specific environment. stated values were obtained by measurement and simulation according to the standards listed below. standards figure 23. surface mount for soic wide body non-exposed pad 28-pin soicw 33889dw dwb suffix eg suffix (pb-free) 98asb42345 28-pin soicw note for package dimensions, refer to the 33889 device datasheet. 33889eg t j = r ja . p table 34. thermal performance comparison thermal resistance [ c/w] ja (1) (2) 42 jb (2) (3) 11 ja (1) (4) 69 ? (5) 23 notes 1. per jedec jesd51-2 at natural convection, still air condition. 2. 2s2p thermal test board per jedec jesd51-7. 3. per jedec jesd51-8, with the board temperature on the center trace near the center lead. 4. single layer thermal test board per jedec jesd51-3. 5. thermal resistance between the die junction and the package top surface; cold plate attached to the package top surface and remaining surfaces insulated. 20 terminal soicw 1.27 mm pitch 18.0 mm x 7.5 mm body
analog integrated circuit device data freescale semiconductor 57 33889 additional documentation thermal addendum (rev 2.0) figure 24. thermal test board device on thermal test board r ja is the thermal resistance between die junction and ambient air. 28-pin soicw 1.27 mm pitch 18.0 mm x 7.5 mm body 33889 pin connections wdog miso sclk gnd gnd gnd gnd canl canh rtl rth v2 cs mosi rx rst int gnd gnd gnd gnd v2ctrl vsup hs1 l0 l1 tx vdd1 4 5 6 7 8 9 10 11 12 13 14 2 3 28 25 24 23 22 21 20 19 18 17 16 15 27 26 1 a material: single layer printed circuit board fr4, 1.6 mm thickness cu traces, 0.07 mm thickness outline: 80 mm x 100 mm board area, including edge connector for thermal testing area a : cu heat-spreading areas on board surface ambient conditions: natural convection, still air table 35. thermal resistance performance thermal resistance area a (mm 2 ) ( c/w) r ja 0 69 300 53 600 48
analog integrated circuit device data 58 freescale semiconductor 33889 additional documentation thermal addendum (rev 2.0) figure 25. device on thermal test board r ja figure 26. transient pin resistance r ja device on thermal test board area a = 600 (mm 2 ) 0 10 20 30 40 50 60 70 80 heat spreading area a [mm2] thermal resistance [oc/w ] 0300 600 r ja x 0.1 1 10 100 1.00e-03 1.00e-02 1.00e-01 1.00e+00 1.00e+01 1.00e+02 1.00e+03 1.00e+04 time[s] thermal resistance [oc/w] r ja x
analog integrated circuit device data freescale semiconductor 59 33889 revision history revision history revision date description of changes 7.0 5/2006 ? implemented revision history page ? added ?eg? pb-free package type ? removed mc33889dw version, and added mc33889b and mc33889d versions ? converted to the freescale format, and updated to the prevailing form and style ? modified device variations between the 33889d and 33889b versions (1) on page 2 ? added thermal addendum (rev 2.0) on page 56 ? changed the maximum ratings on page 6 to the standard format ? added can transceiver description section 8.0 6/2002 ? corrected two instances where pin lo had an overline, and one instance where pin wdog did not. 9.0 8/2006 ? removed mc33889beg/r2 and mc338 89deg/r2 and replaced them with MCZ33889BEG/r2 and mcz33889deg/r2 in the ondering information block 10.0 9/2006 ? replaced the label logic inputs with logic signals (rx, tx, mosi, miso, cs, sclk, rst, wdog, int) on page 6 ? changed cs to cs at various places in the document 11.0 12/2006 ? made changes to supply current in stand-by mode (7),(9) on page 8 and supply current in normal mode (7) on page 8 12.0 3/2007 ? added the e g suffix to the included thermal addendum
mc33889 rev. 12.0 3/2007 information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability ar ising out of the application or use of any product or circuit, and specifically discl aims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale se miconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the fa ilure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemni fy and hold freescale semiconductor and its officers, employees, subsidiaries, affili ates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc., 2007. all rights reserved. rohs-compliant and/or pb-free versions of freescale products have the functionality and electrical characteristics of thei r non-rohs-compliant and/or non-pb-free counterparts. for further information, see http://www.freescale.com or contact your freescale sales representative. for information on freescale?s environmental products program, go to http:// www.freescale.com/epp . how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com

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